1. Technical Field
The present invention relates generally to a semiconductor memory apparatus, and more particularly, to a circuit for driving a word line.
2. Related Art
A semiconductor memory apparatus stores data in memory cells, where gates of the memory cells are controlled by word lines. Thus, the semiconductor memory apparatus includes a word line driving circuit for controlling the word lines.
Generally, a current word line driving circuit has a hierarchical structure for controlling a main word line via the sub word line. The hierarchical structure further refers to a scheme in which a plurality of sub word lines are assigned to one main word line, and adopts a pre-decoding concept. Thus, in order to activate a sub word line for selecting one memory cell, a corresponding main word line and a corresponding sub word line should also be selected.
FIG. 1a is a block diagram showing a conventional word line driving circuit.
The word line driving circuit includes a word line driving signal generator 1 and a sub word line driver 3.
The word line driving signal generator 1 receives an active signal ACT and a precharge signal PCG and generates a main word line enable signal MWLB, a word line boosting signal PX and a word line off signal PXB.
The sub word line driver 3 outputs a sub word line SWL using the word line boosting signal PX as a driving voltage in response to the main word line enable signal MWLB and the word line off signal PXB.
The main word line enable signal MWLB as a signal for selecting a main word line includes as many signals as the number of main word lines. In addition, the word line boosting signal PX and the word line off signal PXB, both needed to select a sub word line, include as many signals as the number of sub word lines assigned to a corresponding main word line. The word line off signal PXB may be generated by inverting the word line boosting signal PX. A plurality of main word lines and a plurality of sub word lines corresponding to a plurality of applied addresses are omitted and instead, one main word line and one sub word line selected by an active signal ACT and a precharge signal PCG are depicted in FIG. 1a. This configuration may be applied to all main word lines and sub word lines.
FIG. 1b is a circuit diagram illustrating an example of the sub word line driver 3 in more detail.
The sub word line driver 3 includes a first PMOS transistor P1 and first and second NMOS transistors N1 and N2.
The first PMOS transistor P1 includes a gate through which the main word line enable signal MWLB is received, a source to which the word line boosting signal PX is connected, and a drain to which the sub word line SWL is connected.
The first NMOS transistor N1 includes a gate through which the main word line enable signal MWLB is received, a source to which a ground voltage VSS is connected, and a drain to which the sub word line SWL is connected.
The second NMOS transistor N2 includes a gate through which the word line off signal PXB is received, a source to which a ground voltage VSS is connected, and a drain to which the sub word line SWL is connected.
FIG. 1c is a waveform diagram illustrating an operation of the sub word line driver 3 in detail.
First, during an active operation, when an active signal ACT is activated, the word line driving generator 1 activates the main word line enable signal MWLB to low and the word boosting signal PX to high. Thus, the word line off signal PXB is output in a deactivated state at the low level. The first PMOS transistor P1 of the sub word line driver 3 is turned on, such that the word line boosting signal PX at the high level is applied to the sub word line SWL.
In contrast, during a precharge operation, when the precharge signal PCG is activated, the word line driving generator 1 deactivates the main word line enable signal MWLB to high and the word boosting signal PX to low. Thus, the word line off signal PXB is set in an activated state at the high level. The first and second NMOS transistors N1 and N2 of the sub word line driver 3 are turned on, such that a voltage level of the sub word line SWL is pulled down to the ground voltage VSS.
Manufacturing defects, such as those pertaining to contacts, may occur in the transistors P1, N1, and N2 of the sub word line driver 3. According to the related art, in order to detect the manufacturing defect, the transistors P1, N1, and N2 are tested by enabling and disabling a sub word line SWL via an active or precharge operation.
However, as shown in section ‘A’ of FIG. 1c, when the precharge operation is performed, the main word line enable signal MWLB and the word line off signal PXB are simultaneously pulled up to the high level, so the first and second NMOS transistors N1 and N2 are turned on at the same time. Thus, it is difficult by the above test operation to check for example, whether only the second NMOS transistor N2, which discharges a voltage of a sub word line, is defective. Existence of this defective transistor would cause an unstable operation of a semiconductor memory apparatus, thus the importance of checking correct operation should be clear.